Memory elements are widely used in computing applications. For example, a typical computing device may include a combination of volatile and non-volatile memory elements to maintain data, program instructions, and the like that are accessed by a processing unit (e.g., a CPU) during operation of the computing device. Latencies associated with memory accesses impair performance of the computing device. Accordingly, a processing unit typically includes one or more memory elements, known as caches, to provide requested data or instructions to the processing unit with reduced latency. Typically, caches are realized as volatile memory elements. For example, an array of static random access memory (SRAM) cells may be used to provide a cache on a common die with the processing unit.
In practice, process, temperature, and voltage (PVT) variations may affect the ability of one or more SRAM cells to be written to and/or read from within a specified timing margin and/or voltage margin. Furthermore, as the size of the components of the SRAM cells decreases, the relative variations across the array of SRAM cells increase. Additionally, component degradation, such as negative bias temperature instability (NBTI), may impact long-term reliability of the SRAM cells and/or the peripheral circuitry utilized to access the SRAM cells.